1. Field of the invention
The present invention relates to a semiconductor chip.
2. Description of the Prior Art
In semiconductor processing, the formation of the passivation layer formed of electrical isolation material on the semiconductor chip is followed as integrated circuits (ICs) within the semiconductor chip and the metallic layer on the surface of the integrated circuits are prepared. Also, openings are made in the passivation layer for allowing the exposure of the underlying metallic layer to function as the bonding pad. Electrical testing can then be performed for selecting out the qualified semiconductor chips those will undergo the packaging process. During testing, a probe is placed in contact with the surface of the bonding pad to electrically test the ICs within the semiconductor chip. Metallic wire bonding is then performed on those passing the electrical testing thus connecting the semiconductor chips to external components. However, the probe must make contact with the bonding pad for performing the electrical testing so a probe mark is often left on the bonding pad of the semiconductor chip. If the probe mark is very deep, peeling occurs during metallic wire bonding. This reduces the reliability of the packaging process.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a top view of a bonding pad 12 on a semiconductor chip 10 according to the prior art. FIG. 2 is a sectional schematic diagram of the bonding pad 12 shown in FIG. 1. After all metallic interconnections and the metallic layer employed as the bonding pad on the semiconductor chip 10 are completed and the circuits are defined, a passivation layer 14 is deposited on the semiconductor chip 10. A hole 16 is then formed on the passivation layer 14 by performing the photolithography and the dry-etching process. After bonding pad processing is complete, the semiconductor chip 10 contains a plurality of bonding pads 12 on its surface and a passivation layer 14 deposited on the bonding pads 12. The passivation layer 14 comprises a plurality of holes 16 separately positioned above each bonding pad 12 thus exposing the metal layer. These holes 16 serve as the testing area of the ICs within the semiconductor chip 10 as well as the connecting area of the metallic wire bonding.
Please refer to FIG. 3. FIG. 3 is a sectional schematic diagram of the bonding pad 12 shown in FIG. 2 after testing. After the bonding pad 12 is completely formed, the electrical testing is performed. A probe is used to contact with the portion of the bonding pad 12 not covered by the passivation layer 14 through the hole 16 for electrically testing the Ics within the semiconductor chip 10. As a result, the qualified semiconductor chips 10 are selected out to be performed the packaging process on later. However, a probe mark 18 remains on the bonding pad 12 where the probe had originally made contact.
Please refer to FIG. 4. FIG. 4 is a schematic diagram of the bonding pad 12 shown in FIG. 3 for bonding to a metallic wire. After successful testing of the semiconductor chip 10, a packaging process is performed in which a metallic wire is attached to the bonding pad 12. When bonding a metallic wire, the rearface of the semiconductor chip 10 is fixed to a baseplate 20 firstly. Next, a metallic ball 24 is formed at one end of the metallic wire 22 and bonded to the exposed metal of the bonding pad 12. The other end of the metallic wire 22 is then dragged to the baseplate 20 and bonded to the predetermined area of the baseplate 20 thus linking the signals of the semiconductor chip 10 to the exterior. The resultant probe mark 18 on the surface of the bonding pad 12 interferes with the adherence of the metallic ball 24 to the bonding pad 12. Also, dragging of the metallic wire 22 may cause the metallic ball 24 to peel from the surface of the bonding pad 12 and even remove part of the metal of the bonding pad 12 with it. This not only causes damage to the surface of the semiconductor chip 10 but also reduces the reliability of the packaging process.